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october 2002 1/17 ? vn610sp single channel high side solid state relay n output current: 45 a n cmos compatible input n proportional load current sense n undervoltage and overvoltage n shut-down n overvoltage clamp n thermal shut down n current limitation n very low stand-by power dissipation n protection against: n loss of ground and loss of v cc n reverse battery protection (*) description the vn610sp is a monolithic device made using stmicroelectronics vipower m0-3 technology. it is intended for driving resistive or inductive loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). this device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio). active current limitation combined with thermal shut-down and automatic restart protect the device against overload. device automatically turns off in case of ground pin disconnection. type r ds(on) i out v cc vn610sp 10m w 45a 36 v 1 block diagram logic undervoltage overvoltage overtemp. i lim pwclamp k i out gnd input v cc output current sense driver v cc clamp v dslim (*) see application schematic at page 9 powerso-10 ? 1 10 order codes package tube t&r powerso-10 ? vn610sp vn610sp 13tr
2/17 vn610sp absolute maximum rating connection diagram (top view) current and voltage conventions symbol parameter value unit v cc dc supply voltage 41 v -v cc reverse dc supply voltage -0.3 v - i gnd dc reverse ground pin current -200 ma i out dc output current internally limited a - i out reverse dc output current -50 a i in dc input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v v esd electrostatic discharge (human body model: r=1.5k w ; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v e max maximum switching energy (l=0.05mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =75a) 193 mj p tot power dissipation at t c < 25c 139 w t j junction operating temperature internally limited c t c case operating temperature -40 to 150 c t stg storage temperature -55 to 150 c i s i gnd v cc v cc v sense output i out current sense i sense input i in v in v out gnd 1 2 3 4 5 6 7 8 9 10 11 output output output output output ground input c.sense n.c. n.c. v cc
3/17 vn610sp thermal data (*) when mounted on a standard single-sided fr-4 board with 50mm 2 of cu (at least 35 m m thick). electrical characteristics (8v 4/17 vn610sp electrical characteristics (continued) current sense (9v v cc 16v) (see figure 2) logic input note 1: v clamp and v ov are correlated. typical difference is 5v. note 2: current sense signal delay after positive input slope. note: sense pin doesnt have to be left floating. symbol parameter test conditions min typ max unit k 1 i out /i sense i out =1.5a; v sense =0.5v; t j = -40c...150c 3300 4400 6000 dk 1 /k 1 current sense ratio drift i out =1.5a; v sense =0.5v; t j = -40c...150c -10 +10 % k 2 i out /i sense i out =15a; v sense =4v; t j =-40c t j =25c...150c 4200 4400 4900 4900 6000 5750 dk 2 /k 2 current sense ratio drift i out =15a; v sense =4v; t j =-40c t j =25c...150c -6 +6 % k 3 i out /i sense i out =45a; v sense =4v; t j =-40c t j =25c...150c 4200 4400 4900 4900 5500 5250 dk 3 /k 3 current sense ratio drift i out =45a; v sense =4v; t j =-40c t j =25c...150c -6 +6 % i sense0 analog sense current vcc=6...16v; i out =0a; v sense =0v; tj=-40c...150c off state; v in =0v on state; v in =5v 0 0 5 10 m a m a v sense max analog sense output voltage v cc =5.5v; i out =7.5a; r sense =10k w v cc >8v; i out =15a; r sense =10k w 3.5 5 v v v senseh analog sense output voltage in overtemperature condition v cc =13v; r sense =3.9k w 5.5 v r vsenseh analog sense output impedance in overtemperature condition v cc =13v; t j >t tsd ; output open 400 w t dsense current sense delay reponse to 90% i sense (see note 2) 500 m s symbol parameter test conditions min typ max unit v il input low level voltage 1.25 v i il low level input current v in =1.25v 1 m a v ih input high level voltage 3.25 v i ih high level input current v in =3.25v 10 m a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in =1ma i in =-1ma 66.8 -0.7 8v v 2
5/17 vn610sp truth table conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 1
6/17 vn610sp electrical transient requirements figure 1: switching characteristics (resistive load r l =0.87 w ) iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 1 v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
7/17 vn610sp 1 figure 2: i out /i sense versus i out i out /i sense i out 0 5 10 15 20 25 30 35 40 45 50 3000 3500 4000 4500 5000 5500 6000 6500 min.tj=-40c max.tj=-40c min.tj=25...150c max.tj=25...150c typical value
8/17 vn610sp 1 1 sense current input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc sense current input sense figure 3: waveforms load current load current load current overtemperature input sense current t tsd t r t j load current v ov v ovhyst v cc > v usd short to ground input load current sense current load voltage input load voltage sense current load current 9/17 vn610sp gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. 1 application schematic v cc gnd output d gnd r gnd d ld m c +5v r prot v gnd input current sense r sense r prot 1
10/17 vn610sp high level input current input clamp voltage off state output current -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 9 il(off1) (a) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma turn-on voltage slope turn-off voltage slope -50 -25 0 25 50 75 100 125 150 175 tc (o c) 250 300 350 400 450 500 550 600 650 700 dvout/dt(on) (v/ms) vcc=13v rl=0.87ohm -50 -25 0 25 50 75 100 125 150 175 0 100 200 300 400 500 600 700 800 900 dvout/dt(off) (v/ms) vcc=13v rl=0.87ohm overvoltage shutdown -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) 1
11/17 vn610sp input hysteresis voltage input low level on state resistance vs t case on state resistance vs v cc input high level -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 ron (mohm) iout=15a vcc=8v; 36v 5 10152025303540 vcc (v) 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 ron (mohm) iout=15a tc= - 40oc tc= 25oc tc= 125oc -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (o c) 0 20 40 60 80 100 120 140 160 ilim (a) vcc=13v 1
12/17 vn610sp maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 1000 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c 1
13/17 vn610sp powerso-10 ? pc board r thj-amb vs pcb copper area in open box free air condition powerso-10 ? thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: from minimum pad lay-out to 8cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c 1
14/17 vn610sp thermal fitting model of a single channel hsd in powerso-10 pulse calculation formula thermal parameter area/island (cm 2 ) footprint 6 r1 (c/w) 0.016 r2 (c/w) 0.06 r3( c/w) 0.08 r4 (c/w) 0.8 r5 (c/w) 12 r6 (c/w) 37 22 c1 (w.s/c) 0.002 c2 (w.s/c) 1.00e-02 c3 (w.s/c) 0.04 c4 (w.s/c) 0.3 c5 (w.s/c) 0.75 c6 (w.s/c) 3 5 z th d r th d z thtp 1 d C () + = where d t p t = powerso-10 thermal impedance junction ambient single pulse 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 6 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 1
15/17 vn610sp dim. mm. inch min. typ max. min. typ. max. a 3.35 3.65 0.132 0.144 a (*) 3.4 3.6 0.134 0.142 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 b (*) 0.37 0.53 0.014 0.021 c 0.35 0.55 0.013 0.022 c (*) 0.23 0.32 0.009 0.0126 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 9.30 9.50 0.366 0.374 e2 7.20 7.60 0.283 300 e2 (*) 7.30 7.50 0.287 0.295 e4 5.90 6.10 0.232 0.240 e4 (*) 5.90 6.30 0.232 0.248 e 1.27 0.050 f 1.25 1.35 0.049 0.053 f (*) 1.20 1.40 0.047 0.055 h 13.80 14.40 0.543 0.567 h (*) 13.85 14.35 0.545 0.565 h 0.50 0.002 l 1.20 1.80 0.047 0.070 l (*) 0.80 1.10 0.031 0.043 a 0o 8o 0o 8o a (*) 2o 8o 2o 8o powerso-10 ? mechanical data (*) muar only poa p013p detail "a" plane seating a l a1 f a1 h a d d1 = = = = e4 0.10 a c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a 1
16/17 vn610sp powerso-10 ? suggested pad layout 1 tape and reel shipment (suffix 13tr) reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed 6.30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0.6 10 9 8 7 6 b a c all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 tube shipment (no suffix) c a b muar casablanca 1
17/17 vn610sp information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 1

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